(1) Field of the Invention
The present invention relates to a process in which Metal Oxide Silicon Field Effect Transistors, (MOSFET), devices are fabricated using specific semiconductor fabrication techniques to improve yield and performance.
(2) Description of Prior Art
Very large scale integration (VLSI) technologies have helped the electronic chip industry reduce cost while still increasing chip and circuit performance. Further improvements in cost and performance strongly depends on the ability of the semiconductor process community to either continue to decrease chip size or use less resistive films.
The advances in lithograhy, such as more advanced cameras, or more sensitive photoresist materials, have allowed important features of semiconductor chips to decrease in size thus improving density as well as performance. The reduction in gate electrode dimensions have resulted in narrower channel lengths of FET devices, thus improving performance. However the narrower polysilicon gates are less conductive than their wider counterparts thus a decrease in performance can result. One method to overcome the resistive aspect of narrower polysilicon gates is via the use of silicided polysilicon gates.
There are several methods for preparing silicided polysilicon gates. One can deposit, either via chemical vapor deposition, (CVD), or vacuum processes, a silicide, such as titanium silicide, (TiSi.sub.2), on a blanket polysilicon layer and use standard lithograhy and RIE processes to define a silicide/polysilicon gate. U.S. Pat. No. 5,089,432, by Yoo, shows this process. The use of this technique does not allow the source and drain regions to benefit from this process, since these regions are defined after the polysilicon gates have been formed. A method that does allow both the polysilicon gate as well as the source and drains to be silicided is a self-aligned process, usually referred to as salicide.
The salicide process is accomplished by depositing a metal, such as titanium, (Ti), on the patterned gate and source-drain. The polysilicon gate had previously been subjected to an insulator/reactive ion etching, (RIE), process to create a insulator sidewall which is needed for this salicide process. When these structures are subjected to an anneal step, TiSi.sub.2 will form only on the exposed silicon regions, such as the top of the polysilicon gate and the source-drain areas. Ti will remain unreacted on non silicon regions, such as the polysilicon insulator sidewall. A selective etch is than used to remove the unreacted Ti, not significantly attacking the TiSi.sub.2, and thus arriving at low resistance silicided gates and source-drains, isolated by the polysilicon insulator sidewall.
One yield detractor associated with the self aligned process is bridging between the polysilicon gate and the source-drain. This arises from either Ti not being removed by the selective etchant, or somehow the anneal process created TiSi.sub.2 on the sidewall and thus the etchant was ineffective. Thus the semiconductor industry is still investigating process sequences that would reduce or eliminate the bridging phenomena.